1. Field of the Invention
This invention relates to the field of integrated circuit testing and in particular to a method for testing long range on-chip counters concurrently with other on-chip circuit tests.
2. Description of the Relevant Art
Integrated circuits (ICs) have found extensive use in all aspects of our society. The ever-increasing manufacturing time in which ICs are produced, coupled with the ever-increasing density and complexity, make ensuring the reliability of ICs an increasing challenge. ICs can suffer from faults caused by numerous imperfections in the fabrication process, and hence they must be tested. The testing is preferably performed at the manufacturing site to prevent shipment of faulty chips and to permit rapid location and elimination of problems in the fabrication process. Due to the quantity and complexity of the ICs to be tested, testing speed is a crucial factor, and it is desirable to minimize test time per chip.
IC chips are often synchronously controlled by a clock signal generated from an oscillator or other source. Various circuitry for generating the clock signal is normally included on the chip, and must also be tested. The generation circuitry typically includes frequency dividers (also referred to as counters) which reduce the oscillator frequency to a desired clock frequency. In many cases, the counters may be chained together to count long intervals. An example of this would be a microprocessor which operates from a crystal oscillator having a frequency of 10 MHz, and which requires an interrupt signal to be generated every 100 ms. For this example, a counter chain is needed to count 10.sup.6 cycles to generate the interrupt.
When counters are chained together, the first stage produces a reduced frequency clock which is coupled to the second stage. The second stage further reduces the clock frequency and subsequent stages repeat this pattern. It is noted that each stage produces a potential clock signal for clocking other on-chip circuitry. Various on-chip circuits may require clocking signals having different frequencies or having specific timing relationships with one another. Hence, it is not uncommon to have chips operating interdependent IC modules at different clock rates. Differing-rate clock signals are easily (and synchronously) available in the counter chain, and coupling to the appropriate stages in a counter chain is a preferred clock generation technique.
Testing a counter chain by running through 10.sup.6 clock cycles would require an unnecessary and undesirable time delay. A faster method for verifying the operation of counter chains is desired. The faster method would preferably be performed in parallel with tests of other IC modules on the chip, and would therefore preferably preserve the timing relationship between clock signals provided at various points in the timing chain.